Parcus: Energy-Aware and Robust Parallelization of AUTOSAR Legacy Applications

Embedded multicore processors are an attractive alternative to sophisticated single-core processors for the use in automobile electronic control units (ECUs), due to their expected higher performance and energy efficiency. Parallelization approaches for AUTOSAR legacy software exploit these benefits. Nevertheless, these approaches focus on extracting performance neglecting the system's worst-case sensor/actuator latency and energy consumption. This paper presents Parcus, an energy-and latency-aware parallelization technique that combines both runnable-and tasklevel parallelism. Parcus explicitly models the traversal of data from sensor to actuator through task instances, enabling to consider the latency imposed by parallelization techniques. The parallel schedule quality (PSQ) metric quantifies the success of the parallelization, for which it takes the latency and the processor frequency into account. We demonstrate the applicability of Parcus with an automotive case study. The results show that Parcus can fully utilize the processor's energy-saving potential.This research received funding from the EU FP7 no. 287519 (parMERASA), the ARTEMIS-JU no. 621429 (EMC2), and the German Federal Ministry of Education and Research.Peer ReviewedPostprint (author's final draft

Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation

Langen D, Niemann J-C, Porrmann M, Kalte H, Rückert U. Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation. In: Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany; 2002.In this paper, an implementation of a RISC processor core for SoC designs is presented. We analyze the differences between a prototypical FPGA implementation and standard cell realizations in an 0.6μm and an 0.13μm technology, respectively. The core was developed by using the hardware description language VHDL, which offers the opportunity of adding special, optimized hardware blocks for various operations. The effects on area and power consumption as well as computational power are analyzed. A detailed overview of the implementation of additional hardware multipliers and their effects on the above mentioned topics concludes this paper

Aktive Router: Ein Hardwarekonzept für Storage Area Networks

Brinkmann A, Langen D, Rückert U. Aktive Router: Ein Hardwarekonzept für Storage Area Networks. In: Proceedings of the ITG Workshop Mikroelektronik für die Informationstechnik. Darmstadt, Germany; 2000: 41-46.Die Verschaltung von Festplatten zu Feldern zur effizienten Verwaltung von riesigen Datenmengen gewinnt immer mehr an Bedeutung. Durch den Einsatz aktiver Einheiten zum Aufbau von internen Verbindungsstrukturen zwischen den Festplatten ist es möglich, an das System angeschlossene Dateiserver von vielen Basisaufgaben zu entlasten. Diese aktiven Router basieren neben einer Routingeinheit und den Schnittstellen zu den Festplatten und den Dateiservern auf einem Mikroprozessor und einer rekonfigurierbaren Einheit. Im Rahmen dieser Arbeit werden mögliche Einsatzgebiete von aktiven Routern, Untersuchungen zu deren Dimensionierung und praktischen Implementierungen der Hardware vorgestellt

A Rapid Prototyping Environment for Microprocessor based System-on-Chips and its Application to the Development of a Network Processor

Brinkmann A, Langen D, Rückert U. A Rapid Prototyping Environment for Microprocessor based System-on-Chips and its Application to the Development of a Network Processor. In: Proceedings of the 10th International Conference on Field Programmable Logic and Applications (FPL 2000). Villach, Austria: Springer Berlin Heidelberg; 2000: 838-841.The rapid advances in microelectronic circuit design have dramatically increased the design complexity of modern integrated devices. One approach to fit the time-to-market requirements is the use of rapid prototyping environments. In this paper we introduce a new FPGA based prototyping environment, on which a full functional embedded system can be implemented. The main distinction to other environments is the incorporation of a synthesizable and configurable microprocessor core into the design space. Furthermore we present the application of this environment to the development of a network processor which consists of a processor core and an Ethernet controller

Abschätzung des Flächen- und Energieverbrauchs von Verbindungsstrukturen auf einem Chip

Langen D, Brinkmann A, Rückert U. Abschätzung des Flächen- und Energieverbrauchs von Verbindungsstrukturen auf einem Chip. In: Proceedings of the ITG Workshop Mikroelektronik für die Informationstechnik. Darmstadt, Germany; 2000: 247-252.Diese Arbeit befaßt sich mit der Aufgabe, den Energie- und Flächenverbrauch von Verbindungsstrukturen auf einem Chip für Standardzellen-Prozesse auf einer hohen Abstraktionsebene abzuschätzen. Es werden analytische Untersuchungen bezüglich der Verbindungsstrukturen Bus, Crossbar-Switch und Multiplexer vorgestellt und mit den Ergebnissen einer Simulation für eine 0,6 μm CMOS Technologie verglichen. Bezüglich der Abschätzung des Energieverbrauchs ergab sich ein mittlerer Fehler von etwa 10%

Source-level timing annotation and simulation for a heterogeneous multiprocessor

A generic and retargetable tool flow is presented that en-ables the export of timing data from software running on a cycle-accurate Virtual Prototype (VP) to a concurrent functional simulator. First, an annotation framework takes information gathered from running an application on the VP and automatically annotates the line-level delays back to the original source code. Then, a SystemC-based timed functional simulator runs the annotated source code much faster than the VP while preserving timing accuracy. This simulator is API-compatible with the multiprocessor’s op-erating system. Therefore, it can compile and run unmodi-fied applications on the host PC. This flow has been imple-mented for MuSIC(Multiple SIMD Cores) [6], a heteroge-neous multiprocessor developed at Infineon to support Soft-ware Defined Radio (SDR). When compared with an op-timized cycle-accurate VP of MuSIC on a variety of tests, including a multiprocessor JPEG encoder, the accuracy is within 20%, with speedups from 10x to 1000x. 1

Parcus: Energy-Aware and Robust Parallelization of AUTOSAR Legacy Applications

Embedded multicore processors are an attractive alternative to sophisticated single-core processors for the use in automobile electronic control units (ECUs), due to their expected higher performance and energy efficiency. Parallelization approaches for AUTOSAR legacy software exploit these benefits. Nevertheless, these approaches focus on extracting performance neglecting the system's worst-case sensor/actuator latency and energy consumption. This paper presents Parcus, an energy-and latency-aware parallelization technique that combines both runnable-and tasklevel parallelism. Parcus explicitly models the traversal of data from sensor to actuator through task instances, enabling to consider the latency imposed by parallelization techniques. The parallel schedule quality (PSQ) metric quantifies the success of the parallelization, for which it takes the latency and the processor frequency into account. We demonstrate the applicability of Parcus with an automotive case study. The results show that Parcus can fully utilize the processor's energy-saving potential.This research received funding from the EU FP7 no. 287519 (parMERASA), the ARTEMIS-JU no. 621429 (EMC2), and the German Federal Ministry of Education and Research.Peer Reviewe

Sex-Related Motor Deficits in the Tau-P301L Mouse Model

The contribution of mouse models for basic and translational research at different levels is important to understand neurodegenerative diseases, including tauopathies, by studying the alterations in the corresponding mouse models in detail. Moreover, several studies demonstrated that pathological as well as behavioral changes are influenced by the sex. For this purpose, we performed an in-depth characterization of the behavioral alterations in the transgenic Tau-P301L mouse model. Sex-matched wild type and homozygous Tau-P301L mice were tested in a battery of behavioral tests at different ages. Tau-P301L male mice showed olfactory and motor deficits as well as increased Tau pathology, which was not observed in Tau-P301L female mice. Both Tau-P301L male and female mice had phenotypic alterations in the SHIRPA test battery and cognitive deficits in the novel object recognition test. This study demonstrated that Tau-P301L mice have phenotypic alterations, which are in line with the histological changes and with a sex-dependent performance in those tests. Summarized, the Tau-P301L mouse model shows phenotypic alterations due to the presence of neurofibrillary tangles in the brai

PEAβ Triggers Cognitive Decline and Amyloid Burden in a Novel Mouse Model of Alzheimer’s Disease

Understanding the physiopathology of Alzheimer’s disease (AD) has improved substantially based on studies of mouse models mimicking at least one aspect of the disease. Many transgenic lines have been established, leading to amyloidosis but lacking neurodegeneration. The aim of the current study was to generate a novel mouse model that develops neuritic plaques containing the aggressive pyroglutamate modified amyloid-β (pEAβ) species in the brain. The TAPS line was developed by intercrossing of the pEAβ-producing TBA2.1 mice with the plaque-developing line APPswe/PS1ΔE9. The phenotype of the new mouse line was characterized using immunostaining, and different cognitive and general behavioral tests. In comparison to the parental lines, TAPS animals developed an earlier onset of pathology and increased plaque load, including striatal pEAβ-positive neuritic plaques, and enhanced neuroinflammation. In addition to abnormalities in general behavior, locomotion, and exploratory behavior, TAPS mice displayed cognitive deficits in a variety of tests that were most pronounced in the fear conditioning paradigm and in spatial learning in comparison to the parental lines. In conclusion, the combination of a pEAβ- and a plaque-developing mouse model led to an accelerated amyloid pathology and cognitive decline in TAPS mice, qualifying this line as a novel amyloidosis model for future studies